High-Speed Analog Layout Engineer
Job Title: High-Speed Analog Layout Engineer Location: Austin, Texas Work Arrangement: To be confirmed (the original requirements mention both remote and onsite work) Experience: 5–12+ years Must-Have Requirement: Hands-on TSMC 4nm process experience Job Overview We are seeking an experienced High-Speed Analog Layout Engineer to design and implement physical silicon layouts for high-frequency and high-speed analog/mixed-signal circuits. The ideal candidate will have extensive experience in custom IC layout, advanced CMOS/FinFET technologies, and layout optimization for performance, signal integrity, and reliability. Candidates must have hands-on experience with the TSMC 4nm process and a strong understanding of high-speed circuit layout, floor planning, parasitic control, and physical verification.
Key Responsibilities
Design and implement custom layouts for high-speed analog and mixed-signal circuits, including SerDes, ADCs, DACs, PLLs, and other high-speed blocks. Develop block-level and chip-level floor plans to support efficient integration and optimal circuit performance. Manage hierarchical block integration and support package-aware or micro-bump co-design requirements. Optimize layouts to minimize parasitic capacitance, resistance, noise, and other layout-dependent effects. Apply advanced layout techniques, including device matching, common-centroid structures, guard rings, isolation, and shielding. Address layout-dependent effects (LDE), including well proximity effect (WPE) and length of diffusion (LOD), where applicable. Implement differential routing, ground shielding, and other noise-reduction techniques to maintain signal integrity. Perform physical verification and ensure closure of Design Rule Check (DRC), Layout Versus Schematic (LVS), Electrical Rule Check (ERC), and antenna rule violations. Support electromigration and IR-drop reliability checks, along with electrostatic discharge (ESD) protection requirements. Collaborate with circuit designers, physical design engineers, verification teams, and other cross-functional stakeholders to resolve layout issues. Ensure layouts meet performance, manufacturability, reliability, and project delivery requirements. Required Qualifications 5–12+ years of hands-on experience in custom IC layout, analog layout, or mixed-signal layout design. Mandatory: Direct hands-on experience with the TSMC 4nm process. Strong experience with advanced CMOS/FinFET semiconductor technologies. Experience designing layouts for high-speed analog and mixed-signal circuits. Proficiency in floor planning, hierarchical integration, device matching, and parasitic optimization. Strong understanding of physical verification processes, including DRC, LVS, ERC, and antenna checks. Experience with EM/IR reliability considerations and ESD protection. Strong analytical, debugging, and problem-solving skills. Ability to collaborate effectively with circuit design and engineering teams.
Preferred Qualifications
Experience with advanced process nodes such as TSMC N3, N4, or N5. Experience with high-speed SerDes, ADC, DAC, PLL, or other performance-critical circuit blocks. Knowledge of package-aware layout, micro-bump integration, and advanced shielding techniques. Experience with industry-standard custom IC layout and physical verification tools. Ideal Candidate Profile The ideal candidate is a hands-on custom IC layout specialist with direct TSMC 4nm experience, a strong background in high-speed analog/mixed-signal circuit layout, and demonstrated expertise in physical verification, parasitic optimization, and advanced-node design requirements. Important: Candidates must be able to confirm their TSMC 4nm experience. Work arrangement and onsite expectations in Austin, Texas, should be confirmed before submission.